1. Field of the Invention
The present invention relates generally to CMOS devices and circuits, and more particularly to methods and apparatus for hardening the same against total dose radiation effects.
2. Description of the Related Art
Radiation can have harmful effects on microelectronics. For years, practitioners have studied the various ways that different types of radiation affect microelectronics, and have attempted to devise ways of eliminating or at least mitigating the problems that these various types of radiation can create for microelectronics. Three major types of ionizing radiation-induced effects are generally recognized as potential interferents with integrated circuits: total dose effects, dose-rate effects, and soft errors (a.k.a. single event effects). Other non-ionizing radiation effects are also well-documented.
Single event effects occur when a high energy particle (such as a cosmic ray, proton, or neutron) changes the state of a particular device in an integrated circuit, thereby causing a loss of information. Single event effects are localized to a particular region of an integrated circuit.
Dose rate effects are caused by the exposure of an entire integrated circuit to a flood of radiation, typically x- or xcex3-rays. These are typically related to a short burst (ns to ms) of high intensity radiation, such as that emitted by a nuclear detonation. Such exposure can cause temporary, and in some cases permanent, failure in integrated circuits.
Total dose effects in CMOS and NMOS devices are related to the permanent failure of an integrated circuit caused by an accumulation of radiation dose. Such failure results from the trapping of holes produced by ionizing radiation in the insulating SiO2 region. This can occur in either the gate oxide or the field oxide regions. In modem devices with very thin gate oxides it is far more likely to be the latter. As the name suggests, total dose effects are related to the entire exposure history of integrated circuitsxe2x80x94when the total dose exceeds some threshold value, circuit failure is observed. This cumulative nature of total dose effects distinguishes them from single event effects and dose rate effects, which are related instead to short term, transient, phenomena.
For modern commercial CMOS devices, it is known that total dose failure is caused by radiation-generated holes becoming trapped in the field oxide. With increasing dose, a region under the field oxide of the n-channel transistor becomes inverted between the source and the drain, resulting in parasitic leakage currents. Note that the NMOS transistors are the most sensitive part of the CMOS circuit to total dose effects.
Efforts have been made to harden CMOS devices and circuits against total dose effects. Methods include implanting ions into and under oxide layers, introducing defects into oxide layers, and thinning oxide layers. However, because of their invasive nature they are difficult to implement with acceptable device yields. Moreover, these methods all add complex steps to the manufacturing process.
Accordingly, it is an object of this invention to provide a simple, cost effective method for mitigating total dose effects in CMOS circuits.
It is a further object of this invention to achieve this mitigation without changing the layer structure of the device, such as layer thinning, implantation, or damaging the layers, so that the high performance of the circuit is maintained.
These and additional objects of the invention are accomplished by the structures and processes hereinafter described.
An aspect of the present invention is a CMOS or NMOS device having one or more n-channel FETs disposed on a substrate, the device being resistant to total dose radiation failures, the device further including a negative voltage source, for applying a steady negative back bias to the substrate of the n-channel FETs to mitigate leakage currents in the device, thereby mitigating total dose radiation effects.
Another aspect of the present invention is a method for operating a CMOS or NMOS device to resist total dose radiation failures, the device having one or more n-channel FETs disposed on a substrate, including the steps: (a) disposing the CMOS or NMOS device in a radiation environment, the radiation environment delivering a dose on the order of tens or hundreds of krad (Si) over the period of use of the CMOS device; and (b) applying a steady negative back bias to the substrate of the NMOS FETs, at a voltage for mitigating leakage currents about the n-channel FETs.